Verilog-A Support The Verilog-A feature of T-Spice allows designers to describe and simulate analog circuits behaviorally. For analog designers, Verilog-A enables a top-down approach to circuit design, and allows co-simulation between behavioral blocks and device level analog SPICE netlists. For process developers especially TFT and MEMS process, Verilog-A provides an efficient language for describing device behavior, which is portable across simulators. T-Spice is compliant with all Verilog-A specifications in the latest standard Verilog-AMS LRM (Language Reference Manual) version 2.2, passes the Compact Model Council test suite, and is fully compatible with Spectre®, H-Spice®, and SmartSpice®. User Interface Improvements Simulations now operate on the active Spice file. Filenames of output files are auto-generated from the input filename, and can be optionally placed in a new folder with a time stamped name each time the simulation is run. This allows input files or result files to be easily compared in W-Edit or a 3rd party differencing program. L-Edit L-Edit enables analog/mixed-signal designers to automate the layout of similar circuits for different ICs. It meets your needs by combining the fastest rendering available with powerful features. You can get started with minimal training, and draw and edit quickly with fewer keystrokes and mouse clicks than in other layout tools.